And it does not concern you that this RVA profile is version 23
Not sure where you got that information. There are only 5 RISC-V profiles.
And they are incompatible, with version 23 because they lack instructions?
Like all the x86 CPUs from a few years ago that don’t have all the new extensions? Not supporting new extensions doesn’t mean the CPU is useless, only that it’s worse than new ones, as things should be when there’s progress. Or I guess you throw out your x86 CPU every time Intel/AMD create a new instruction?
So a compiler would have to support at least a certain number of those profiles
Do you think compilers only target one x86 version with one set of instructions? For example in x86, there’s SIMD versions SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, compilers support all of them, and that’s literally just for the SIMD instructions. What’s new?
Yes, there are differences in certain x86 command sets. But they actually have a market. RISC-V is just a niche, and splintering in a small niche is making the support situation worse.
Not sure where you got that information. There are only 5 RISC-V profiles.
Like all the x86 CPUs from a few years ago that don’t have all the new extensions? Not supporting new extensions doesn’t mean the CPU is useless, only that it’s worse than new ones, as things should be when there’s progress. Or I guess you throw out your x86 CPU every time Intel/AMD create a new instruction?
Do you think compilers only target one x86 version with one set of instructions? For example in x86, there’s SIMD versions SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, compilers support all of them, and that’s literally just for the SIMD instructions. What’s new?
Yes, there are differences in certain x86 command sets. But they actually have a market. RISC-V is just a niche, and splintering in a small niche is making the support situation worse.
The support situation is so bad that both GCC and LLVM have extensive for RISC-V.